1. Field of the Invention
The present invention relates to a wafer processing method by which a wafer provided with a plurality of streets in a grid pattern on a surface thereof and provided with devices formed in a plurality of regions demarcated by the plurality of streets is divided along the streets.
2. Description of the Related Art
In a semiconductor device manufacturing process, for example, such devices as ICs and LSIs are formed in a plurality of regions demarcated by planned dividing lines (streets) formed in a grid pattern on a surface of a semiconductor wafer, which has a roughly circular disk-like shape, and the regions provided with the devices are divided along the streets to thereby manufacture the individual semiconductor devices. As the dividing apparatus for dividing the semiconductor wafer, in general, a cutting apparatus is used. In using the cutting apparatus, the semiconductor wafer is cut along the streets by a cutting blade having a thickness of about 30 μm. The semiconductor devices thus divided are respectively packaged, to be used widely for electric apparatuses such as cell phones and personal computers.
In recent years, the electric apparatuses such as cell phones and personal computers have been demanded to be reduced in weight and size, and, for this purpose, there is a demand for thinner semiconductor devices. As a technology for dividing the semiconductor devices with smaller thickness, a dividing technology generally called “dicing before grinding” has been put to practical use. The dicing-before-grinding method is a technology in which cut grooves having a predetermined depth (a depth corresponding to the finished thickness of semiconductor devices) are formed from the face side of the semiconductor wafer along the streets, and thereafter the back side of the semiconductor wafer provided with the cut grooves on the face side is ground to expose the cut grooves, thereby dividing the semiconductor wafer into the individual semiconductor devices; by this technology, the semiconductor devices can be processed to a thickness of 50 μm or below (see, for example, Japanese Patent Laid-open No. Hei 11-40520).